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CXD2930BR
GPS LSI with Built-in 32-bit RISC CPU
Description The CXD2930BR is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, RAM, UART, timer, etc. This LSI, used together with an external ROM and RF LSI (CXA1951AQ), enables the configuration of a 3-chip system capable of measuring its position anywhere on the globe. 144 pin LQFP (Plastic)
Features * 16-channel GPS receiver capable of simultaneously receiving 16 satellites * Supports DARC system FM multiplexed differential GPS * All-in-view measurement * 2-satellite measurement * Timer supporting GPS time * High performance 32-bit RISC CPU * 32K-byte RAM * 3-channel UART * Baud rate generator * Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and 38.4K baud * Supports 1/2/4-byte buffer mode * 23-bit general-purpose I/O port capable of defining input/output independently for each bit Structure Silicon gate CMOS IC Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature Topr -40 to +85
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98307A96-PS
CXD2930BR
Performance * Reception frequency 1575.42MHz (L1 band, CA code) * Reception sensitivity (using the CXA1951AQ in the RF block) Antenna -130dBm or less * Time to first fix (time until initial measurement after power-on) CXA1951AQ Cold start (without ephemeris and almanac) RF Converter 35 to 60s Warm start (without ephemeris with almanac) 0V 0V 34 to 50s TCXO IF Hot start (with ephemeris and almanac) TXD 6 to 20s CXD2930BR Reacquisition time (interrupt recovery time) 16ch GPS Processor RXD Less than 5 minutes: < 3 to 6s 5 minutes or more: < 6 to 10s * Positioning accuracy Flash ROM Stand alone (GPS unit only) 2M bit 1 : < 30m 3 : < 90m GPS Receiver System Diagram Using the CXD2930BR DGPS (differential GPS) 1 : < 6m 3 : < 18m * Measurement data update time Every 1s * Communication method Sony standard serial communication Supports NMEA The noted values may be exceeded depending on the operating environment and other conditions. The above performance values are as of February 1998. Sony reserves the right to change performance without prior notice. Accordingly, the above performance values should be used only as reference data.
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CXD2930BR
Block Diagram
DCS0 to 5/PORT (16:21)
DADR (0:15)
IADR (0:18)
IB (0:15)
DB (0:7)
ICS0, 1
XCS0
DWR
DRD
IWR
IRD
TEST0 to 1 BIU PORT (0:15) RUN HOLD NMI PMI INBKOR HOLDA SINT/PORT (22) 32K Byte SRAM 32 bit RISC COSEL MCKI MCKO CLKOUT EXRS PWRST VDD x 10 VSS x 10
TXD0 to 2 RXD0 to 2
UART (Baud Rate Generator) x 3
TIMER x 3 AVD 16ch GPS DSP 8bit ADC AVS VRT VRB
IF0O
CCKO
CCKI
INHI
XTCXO
OTCXO
TCXO
IF1
IF0
INLW
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AVIN
CXD2930BR
Pin Configuration
DADR15
DADR14
DADR13
DADR12
DADR10
DADR11
DADR9
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
XCS0
DWR
DRD
IB13
IB12
IB15
IB14
IB10
IB11
DB4
DB3
DB2
DB0
DB5
DB1
VDD
VDD
VSS
VSS
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
IB9 72 IB8 71 IB7 70 VSS 69 IB6 68 IB5 67 IB4 66 IB3 65 IB2 64 IB1 63 VDD 62 IB0 61 IADR18 60 IADR17 59 IADR16 58 IADR15 57 IADR14 56 IADR13 55 VSS 54 IADR12 53 IADR11 52 IADR10 51 IADR9 50 IADR8 49 IADR7 48 IADR6 47 VDD 46 IADR5 45 IADR4 44 IADR3 43 IADR2 42 IADR1 41 IADR0 40 ICS1 39 VSS 38 ICS0 37 IRD IWR
DB6 109 DB7 110 SINT/PORT22 111 DCS0/PORT21 112 VDD 113 DCS1/PORT20 114 DCS2/PORT19 115 DCS3/PORT18 116 DCS4/PORT17 117 DCS5/PORT16 118 PORT15 119 PORT14 120 VSS 121 PORT13 122 PORT12 123 PORT11 124 PORT10 125 PORT9 126 PORT8 127 PORT7 128 VDD 129 PORT6 130 PORT5 131 PORT4 132 PORT3 133 PORT2 134 PORT1 135 PORT0 136 VSS 137 TXD2 138 RXD2 139 TXD1 140 RXD1 141 TXD0 142 RXD0 143 VDD 144
1 AVD
2 AVIN
3 VRT
4 VRB
5 AVS
6 VSS
7 TCXO
8 XTCXO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 COSEL CLKOUT VDD OTCXO TEST0 TEST1 CCKI CCKO VSS INHI INLW IF0 IF0O IF1 VDD HOLD NMI PMI INBKOR PWRST VSS MCKI MCKO VDD HOLDA EXRS RUN
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CXD2930BR
Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol AVD AVIN VRT VRB AVS VSS TCXO XTCXO VDD OTCXO TEST0 TEST1 CCKI CCKO VSS INHI INLW IF0 IF0O IF1 VDD HOLD NMI PMI HOLDA INBKOR EXRS PWRST VSS MCK MCKO COSEL CLKOUT I/O -- I I I -- I I O -- O I I I O -- I I I O I -- I I I O O I I -- I O I O A/D converter power supply. Analog input. Reference input. A/D converter GND. GND TCXO binary conversion circuit/crystal oscillator. Power supply. TCXO clock output. Test. Fixed to low level. Description
Timer oscillation circuit. (32.768kHz 100ppm) GND Fixed to low level. Fixed to low level. IF signal binary conversion circuit. IF signal input 1. Input the binary-converted input signal. Power supply. Hold input signal. Hold when high level. Non maskable interrupt. Power management interrupt. Hold acknowledge signal. Break signal for debugging. Reset input signal. Connect to main power supply. Leave open during backup. GND CPU clock oscillation circuit. CPU clock select signal. Selects TCXO clock when low level; MCK clock when high level. CPU clock output.
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CXD2930BR
Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Symbol VDD RUN IWR IRD ICS0 VSS ICS1 IADR0 IADR1 IADR2 IADR3 IADR4 IADR5 VDD IADR6 IADR7 IADR8 IADR9 IADR10 IADR11 IADR12 VSS IADR13 IADR14 IADR15 IADR16 IADR17 IADR18 IB0 VDD IB1 IB2 IB3 IB4 IB5 IB6
I/O -- O O O O -- O O O O O O O -- O O O O O O O -- O O O O O O O -- I/O I/O I/O I/O I/O I/O -6- Data bus I/O for instruction ROM. (MSB) GND Power supply. Power supply.
Description
Signal output indicating CPU operating status. Write signal output for instruction ROM. Read signal for instruction ROM. Chip select 0 for instruction ROM. GND Chip select 1 for instruction ROM. (LSB)
Address signal for instruction ROM.
Address signal for instruction ROM.
Address signal for instruction ROM.
(LSB) Data bus I/O for instruction ROM. Power supply.
CXD2930BR
Pin No. 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 VSS IB7 IB8 IB9
Symbol
I/O -- I/O I/O I/O I/O -- I/O I/O I/O I/O I/O O O O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- (MSB) GND -7- Power supply. (MSB) Data bus I/O for instruction ROM. Power supply. Data bus I/O for instruction ROM. GND
Description
IB10 VDD IB11 IB12 IB13 IB14 IB15 DRD DWR XCS0 DADR0 DADR1 VSS DADR2 DADR3 DADR4 DADR5 DADR6 DADR7 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 VSS
Read signal for external expansion data memory. Write signal for external expansion data memory. Chip select signal for external expansion data memory. (LSB) Address I/O for external expansion data memory. GND
Address I/O for external expansion data memory.
Address I/O for external expansion data memory.
CXD2930BR
Pin No. 105 106 107 108 109 110 111
Symbol DB2 DB3 DB4 DB5 DB6 DB7 SINT/PORT22
I/O I/O I/O I/O I/O I/O I/O I/O (MSB) (LSB)
Description
Data bus I/O for external expansion data memory.
External interrupt input signal/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Chip select for external expansion data memory/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Power supply.
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
DCS0/PORT21 I/O VDD --
DCS1/PORT20 I/O DCS2/PORT19 I/O DCS3/PORT18 I/O DCS4/PORT17 I/O DCS5/PORT16 I/O PORT15 PORT14 VSS PORT13 PORT12 PORT11 PORT10 PORT9 PORT8 PORT7 VDD PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -8- General-purpose I/O port. Power supply. General-purpose I/O port. General-purpose I/O port. GND Chip select for external expansion data memory/general-purpose I/O port. These pins can be used as general-purpose I/O ports according to the internal registers.
CXD2930BR
Pin No. 137 138 139 140 141 142 143 144 VSS
Symbol
I/O -- O I O I O I -- GND
Description
TXD2 RXD2 TXD1 RXD1 TXD0 RXD0 VDD
UART transmission data output (channel 2). UART reception data input (channel 2). UART transmission data output (channel 1). UART reception data input (channel 1). UART transmission data output (channel 0). UART reception data input (channel 0). Power supply.
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CXD2930BR
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to 4.6 * Input voltage VI VSS - 0.5 to VDD + 5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Operating temperature Topr -40 to +85 * Storage temperature Tstg -55 to +150 I/O Pin Capacitance * Input capacitance * Output capacitance * I/O capacitance
V V V C C
CIN COUT CI/O
9 (Max.) 11 (Max.) 11 (Max.)
pF pF pF
Electrical Characteristics Item Input voltage (1) (CMOS level) Input voltage (2) (5V interface) Output voltage (1) High level Low level High level Low level High level Low level Output voltage (2) High level Low level Output voltage (3) High level Low level Current consumption in standby mode Supply current Symbol VIH (1) VIL (1) VIH (2) VIL (2) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) ISTB IDD IOH = -4.0mA IOL = 4.0mA IOH = -8.0mA IOL = 8.0mA Conditions Min.
(VDD = 3.0 to 3.6V, Topr = -40 to +85C) Typ. Max. VDD 0.2VDD 0.7VDD 5.5 0.2VDD VDD - 0.4 0.4 VDD - 0.4 0.4 Unit V V V V V V V V V 0.4 20 4 55 70 50 V A mA Applicable pins 1 2 3 4 5
0.7VDD
IOH = -12.0mA VDD - 0.4 IOL = 12.0mA VDD = 3V VDD = 1.5V f = 18.414MHz
Applicable pins 1 Pins 11, 12, 16, 17, 20, 22, 23, 24, 32 2 Pins 62, 64 to 69, 72 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136, 139, 141, 143 3 Pins 10, 25, 26, 33, 35, 41 to 46, 48 to 54, 56 to 61, 81 to 83, 138, 140, 142 4 Pins 38, 40, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136 5 Pins 36, 37
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CXD2930BR
Electrical Characteristics (IF and TCXO binary conversion pins) (VDD = 3.0 to 3.6V, Topr = -40 to +85C) Item Logical Vth Input amplitude Symbol LVth VIN f = 50MHz, sin wave 0.8 Conditions Min. Typ. VDD/2 Max. Unit V Vp-p Applicable pins Pins 7, 18
Electrical Characteristics (Crystal oscillator) Item Logical Vth Input voltage High level Low level High level Low level Symbol LVth VIH VIL VOH VOL IOH = -3mA IOL = 3mA Conditions
(VDD = 3.0 to 3.6V, Topr = -40 to +85C) Min. Typ. VDD/2 0.7VDD 0.2VDD VDD/2 VDD/2 Max. Unit V V V V V Pin 31 Pin 30 Applicable pins
Output voltage
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CXD2930BR
AC Characteristics (1) When inputting a pulse to the TCXO pin (VDD = 3.0 to 3.6V, Topr = -40 to +85C) When inputting a binary-converted signal
1/fTCK tTH TCXO tTL
Item TCXO clock frequency TCXO clock pulse width
Symbol fTCK
Min. Typ. - 3ppm 24.5
Typ. 18.414
Max. Typ. + 3ppm 29.9
Unit MHz ns
tTH, tTL
When performing binary conversion with the TCXO and XTCXO pins (Pins 7 and 8)
0.01F 0.8Vp-p or more VDD/2 7
1M
8
(2) When performing self-oscillation with the CCKI and CCKO pins (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
220pF 13
10M 220pF 32.768kHz 100ppm 14
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CXD2930BR
(3) IF signal input (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
0.01F 0.8Vp-p or more VDD/2 18
1M
19
(4) When performing self-oscillation with the MCKI and MCKO pins (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
15pF 30
Crystal 15pF
1M
31
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CXD2930BR
Battery Backup Mode The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clocks are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and the registers are initialized. Battery backup mode is canceled by setting power-on reset to high.
10 clocks Power-on reset EXRS PWRST 100ms or more Timer clock CCKI, CCKO Other clocks TCXO, XTCXO, MCKI, MCKO
Normal outputs TXD0 to 2, OTCXO, OSO1 to 2, HOLDA Tri-state outputs INBKOR, RUN, CLKOUT Tri-state outputs ICS0, ICS1, IADR [18:0], IRD, IWR, DRD, DWR, XCS0 Bidirectional (Input) (Output) SINT, IB [15:0], DCS0 to 5, DADR [15:0] DB [7:0], PORT [15:0] Inputs RXD0 to 2, ITCXO, IF0 to 2, OSI1, HOLD, NMI, PMI, DREADY
Fixed low
Fixed low
Hi-Z
Fixed low Hi-Z
Fixed low
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CXD2930BR
CXD2930BR Startup and Initialization The CXD2930BR operation is started by setting the reset input signal EXRS (Pin 30) to high level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset) VDD = 3.0 to 3.6V, Topr = -40 to +85C
VDD Power supply, PWRST (Pin 28) EXRS (Pin 27) 100ms or more VDD/2
VDD [V]
GND
The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST signal should be left open during battery backup. 2. Initialization during operation VDD = 3.0 to 3.6V, Topr = -40 to +85C
Power supply, PWRST (Pin 28) VDD EXRS (Pin 27) VDD [V] 100s or more VDD/2
GND
The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for 100s or more. Keep the PWRST (Pin 28) signal at high level at this time.
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CXD2930BR
External Command Fetch Timing
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h)
Item Read cycle time (Fex: @9.207MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time
Min. -- -- 2 2 1 1 8 0
Typ. 108 -- -- -- -- -- -- --
Max. -- 5 10 9 3 5 -- --
Unit ns ns ns ns ns ns ns ns
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CXD2930BR
External Data Access Timing (ICS0, ISC1) (1) Read (half-word access)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
(2) Write (half-word access)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (i) IWR (k) IB (16) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l)
Item Read/write cycle time (Fex: @9.207MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 17 -
Min. -- -- 2 2 1 1 8 0 0 0 -- 5
Typ. 108 -- -- -- -- -- -- -- -- -- -- --
Max. -- 5 10 9 3 5 -- -- 1 2 5 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
CXD2930BR
(3) Read (word access)
CLKOUT
IADR
ICS0, ICS1
IRD IB H (16) L (16)
(4) Write (word access)
CLKOUT
IADR
ICS0, ICS1
IWR IB L (16) H (16)
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CXD2930BR
External Data Access Timing (XCS0, DCS0 to 5, no data wait) (1) Read (byte access, no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to 5 (e) DRD (g) DB (8) (h) (f) (d)
(2) Write (byte access, no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to 5 (i) DWR (k) DB (8) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l)
Item Read/write cycle time (Fex: @9.207MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 19 -
Min. -- -- 4 4 2 3 16 0 0 0 -- 5
Typ. 108 -- -- -- -- -- -- -- -- -- -- --
Max. -- 9 13 13 8 10 -- -- 1 2 7 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
CXD2930BR
(3) Read (half-word access, no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB H (8) H (8)
(4) Write (half-word access, no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB L (8) H (8)
(5) Read (word access, no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access, no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB LL (8) LH (8) HL (8) HH (8)
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CXD2930BR
External Data Access Timing (XCS0, DCS0 to 5, with data wait) (1) Read (byte access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB (8)
(2) Write (byte access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB (8)
(3) Read (half-word access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB H (8) L (8)
(4) Write (half-word access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB L (8) H (8)
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CXD2930BR
(5) Read (word access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access, with data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB LL (8) LH (8) HL (8) HH (8)
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CXD2930BR
Description of Application Circuit See the Application Circuit when using the CXD2930BR to configure a GPS receiver. Points for caution are as follows. 1. Unused pins Software processing is performed to prevent undesired current from flowing to unused pins in the circuit diagram, so leave these pins open. 2. TCXO input The TCXO frequency is 18.414MHz 3ppm. Signals that have not been binary-converted should be input with an amplitude of 0.8Vp-p or more via a DC filter capacitor (C19 in the circuit diagram). Input binaryconverted signals directly to Pin 7 (TCXO) without passing through C19 or R1 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 3. IF input The CXD2930BR interface is 1.023MHz, and does not accept other frequencies. Signals that have not been binary-converted should be input with an amplitude of 0.8Vp-p or more via a DC filter capacitor (C20). Input binary-converted signals directly to Pin 18 (IF0) without passing through C20 or R3 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 4. TXD (SIO output) The TXD amplitude low level is 0.4V or less, and the high level is VDD - 0.4V (VDD = 3.0 to 3.6V) or more. When the LSI, etc., connected to TXD operates at 5V and has a CMOS input level, perform 3 to 5V conversion before inputting the signal. 5. Real-time clock The current software version uses an external real-time clock. Consult your Sony representative beforehand when using the internal real-time clock. When using an external real-time clock, connect Pin 13 (CCKI) to GND. 6. External program ROM Use a 2M- or 4M-bit external program ROM (IC2) with an access time of 100ns or less and which is capable of 16-bit read.
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Application Circuit
VSS VDD VDD VSS IB (15:0) C1 0.1 C2 0.1
IB11
IB15
IB14
IB13
VSS
VDD
VSS
VDD
IB9
DB5
DB4
DB3
DB2
DB1
DB0
IB15
IB14
IB13
IB12
XCS0
DWR
DRD
IB11
IB10
DADR9
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
IB8 72 IB7 71 VSS 70 IB6 69 IB5 68 IB4 67 IB3 66 IB2 65 IB1 64 VDD 63 IB0 62 IB0 IADR18 IADR17 IADR16 C4 0.1 IB2 IB1 IB3 IB4 IADR18 IADR8 IADR7 IADR6 IADR5 IADR4 IADR3 IB5 IB6 IB7
DADR15
DADR14
DADR13
DADR12
DADR11
109 DB6 110 DB7 111 SINT/PORT22 112 DCS0/PORT21 113 VDD C3 0.1 114 DCS1/PORT20 115 DCS2/PORT19 116 DCS3/PORT18 117 DCS4/PORT17 118 DCS5/PORT16 119 PORT15 120 PORT14 121 VSS 122 PORT13 123 PORT12 124 PORT11 125 PORT10 126 PORT9 127 PORT8 128 PORT7 129 VDD IC1 CXD2930BR
DADR10
IB8
IC2 29LV400T-90 1 NC 2 RY/BY 3 A17 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 IADR2 RESET 44 WE 43 A8 42 A9 41 A10 40 A11 39 A12 38 A13 37 A14 36 IADR9 IADR10 IADR11 IADR12 IADR13 IADR14 IADR15
Recommended components IC1: CXD2930BR IC2: Flash memory Made by Fujitsu and INTEL, 2M- or 4M-bit, access time of 100ns or less (3V and 5V operation) IC3: Real-time clock Made by RICOH (RS5C313) IC4: Voltage regulator (for step-down transformation) Made by SEIKO INSTRUMENTS (S81218SG, steps down 3V to 1.8V) TCXO: Made by Tokyo Denpa Oscillator frequency: 18.414MHz 3ppm
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 IB12 IB10 IB9 IADR18 61 IADR17 60 IADR16 59 IADR15 58 IADR14 57 IADR13 56 VSS 55 IADR12 54 IADR11 53 IADR10 52 IADR9 51 IADR8 50 IADR7 49 IADR6 48 VDD 47 IADR5 46 IADR4 45 IADR3 44 IADR2 43 IADR1 42 IADR0 41 ICS1 40 VSS 39 ICS0 38 IRD 37 MCKO COSEL CLKOUT CCKI CCKO VSS INHI INLW IF0 IF0O IF1 VDD HOLD NMI PMI HOLDA INBKOR EXRS PWRST VSS MCKI VDD RUN IWR IADR5 IADR4 IADR3 IADR2 IADR1 IADR (18:1) C7 0.1 IADR12 IADR11 IADR10 IADR9 IADR8 IADR7 IADR6 IB0 IB8 IB1 IB9 IB2 IB10 IB3 IB11 10 A1 IADR15 IADR14 IADR13 IADR1 11 A0 12 CE 13 GND 14 OE 15 DQ0 16 DQ8 17 DQ1 18 DQ9 19 DQ2 20 DQ10 21 DQ3 22 DQ11
VDD A15 35 A16 34 BYTE 33 GND 32 DQ15 31 DQ7 30 DQ14 29 DQ6 28 DQ13 27 DQ5 26 DQ12 25 DQ4 24 VCC 23 C8 0.1 IB15 IB7 IB14 IB6 IB13 IB5 IB12 IB4 IADR16 IADR17 VDD VSS VSS
NC
NC
VOUT
VIN
GND
AVD
AVIN VRT
VRB AVS VSS
TCXO
XTCXO VDD
OTCXO TEST0
C10 0.1 1 2 3 4 5 6 7 8
3.6V
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
TXD R1 1M VDD VSS VDD
2 R3 1M
RXD
3
VDD
VSS
VSS
TCXO (18.414MHz)
4
IF (1.023MHz) C13 0.1
5
VDD
D2 RB400D-T146
R2 10M X2 32.768k C14 0.1 C19 0.01 C15 C16 220p 220p When using the internal timer
RESET
6
TEST1
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When using an external timer IC4 RS5C313 132 PORT4 133 PORT3 134 PORT2 135 PORT1 136 PORT0 137 VSS 138 TXD2 139 RXD2 140 TXD1 141 RXD1 142 TXD0 143 RXD0 144 VDD INT OSCO SIO 3 OSCI SCL 2 VDD CE 1 VSS 4 131 PORT5 C5 0.1 130 PORT6 C17 0.1 C20 0.01
IC3 5812185G
5
4
3
2
1
X1 5 32.768k C6 6 10p 7 C9 8 10p
D1 RB400D-T146
BT1 3.0V
TXD0
RXD0
CN1
GND
7
VSS
C18 0.1
TCXO
C11 3.3
IF RESET
Input 3.6V in consideration of voltage step-down by diode (D2).
CXD2930BR
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD2930BR
Package Outline
Unit: mm
144PIN LQFP (PLASTIC)
22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 1.4 0.1
72
B
A 144 37
1
0.5
36 0.22 0.05 0.08 M S S
0.1
S
0.1 0.05 0.22 0.05
(21.0)
0 to 10 DETAIL A
0.5 0.15
0.145 0.03
(0.2)
(0.125)
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.3 g
SONY CODE EIAJ CODE JEDEC CODE
LQFP-144P-L01 LQFP144-P-2020
LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
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